Altium

Design Rule Verification Report

Date: 5/18/2022
Time: 6:19:47 PM
Elapsed Time: 00:00:06
Filename: C:\Users\a0498813\Documents\Daughter card\PMP23249_PFC_GaN_DC.PcbDoc
Warnings: 0
Rule Violations: 135

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=16mil) ((OnMultiLayer Or OnMid) And InNetClass('VHV')),(OnMid And Not InNetClass('VHV')) 0
Clearance Constraint (Gap=60mil) (InNetClass('VSWNET') and OnCopper),(Not InNetClass('VSWNET') and OnCopper) 0
Clearance Constraint (Gap=16mil) ((OnMultiLayer Or OnMid) And Not InNetClass('VSWNET')),(OnMid And InNetClass('VSWNET')) 0
Clearance Constraint (Gap=16mil) ((OnMultiLayer Or OnMid) And Not InNetClass('VHV')),(OnMid And InNetClass('VHV')) 0
Clearance Constraint (Gap=6mil) (All),(All) 0
Clearance Constraint (Gap=60mil) (InNetClass('INGND') and OnCopper),(Not InNetClass('INGND') and Not InNetClass('PGND')and OnCopper) 0
Clearance Constraint (Gap=60mil) (InNetClass('VHV')),(Not InNetClass('VHV')) 0
Clearance Constraint (Gap=20mil) (InNet('NC6')),(All) 0
Clearance Constraint (Gap=16mil) ((OnMultiLayer Or OnMid) And InNetClass('VSWNET')),(OnMid And Not InNetClass('VSWNET')) 0
Clearance Constraint (Gap=20mil) (InNet('NC5')),(All) 0
Clearance Constraint (Gap=60mil) (InNetClass('Screw')),(Not OnLayer('Top Layer') AND Not InNetClass('Screw')) 0
Clearance Constraint (Gap=60mil) (InNetClass('Screw')),(OnLayer('Bottom Layer') And Not InNetClass('Screw')) 0
Clearance Constraint (Gap=60mil) (InNetClass('Screw')),(OnLayer('Top Layer') And Not InNetClass('Screw')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=1000mil) (Preferred=10mil) (All) 0
SMD To Corner (Distance=3mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=4.5mil) (IsVia and InAnyComponent) 0
Minimum Annular Ring (Minimum=4.5mil) (IsVia) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=6mil) (Max=251mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 83
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All) 52
Silk to Silk (Clearance=0mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (OnCopper) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 135

Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (1.339mil < 3.937mil) Between Pad C11-2(2036.929mil,1820mil) on Top Layer And Via (2000mil,1795mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.339mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C13-1(1983.622mil,1150mil) on Top Layer And Pad R5-2(1983.622mil,1180mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C13-2(1936.378mil,1150mil) on Top Layer And Pad R5-1(1936.378mil,1180mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C15-1(1983.622mil,1015mil) on Top Layer And Pad C17-1(1983.622mil,1045mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C15-2(1936.378mil,1015mil) on Top Layer And Pad C17-2(1936.378mil,1045mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C16-1(1983.622mil,1740mil) on Top Layer And Pad R6-1(1983.622mil,1710mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (2.441mil < 3.937mil) Between Pad C16-2(1936.378mil,1740mil) on Top Layer And Pad R6-2(1936.378mil,1710mil) on Top Layer [Top Solder] Mask Sliver [2.441mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Pad C2-1(1145mil,1640mil) on Top Layer And Via (1185mil,1665mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.693mil < 3.937mil) Between Pad C3-2(2438.622mil,1645mil) on Top Layer And Via (2470mil,1645mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.693mil]
Minimum Solder Mask Sliver Constraint: (3.042mil < 3.937mil) Between Pad C4-1(2401.378mil,1215mil) on Top Layer And Via (2370mil,1235mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [3.042mil]
Minimum Solder Mask Sliver Constraint: (1.693mil < 3.937mil) Between Pad C7-2(2045mil,1583.622mil) on Top Layer And Via (2040mil,1615mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.693mil]
Minimum Solder Mask Sliver Constraint: (2.52mil < 3.937mil) Between Pad D2-2(1150mil,1030.532mil) on Top Layer And Via (1165mil,1065mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [2.52mil]
Minimum Solder Mask Sliver Constraint: (1.23mil < 3.937mil) Between Pad U1-6(1062.598mil,1569.134mil) on Top Layer And Via (1040mil,1540mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.23mil]
Minimum Solder Mask Sliver Constraint: (1.05mil < 3.937mil) Between Pad U2-5(2111.732mil,1260mil) on Top Layer And Via (2070mil,1245mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.05mil]
Minimum Solder Mask Sliver Constraint: (0.378mil < 3.937mil) Between Pad U3-1(2097.716mil,1747.5mil) on Top Layer And Via (2055mil,1750mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.378mil]
Minimum Solder Mask Sliver Constraint: (1.477mil < 3.937mil) Between Pad U3-3(2097.716mil,1697.5mil) on Top Layer And Via (2055mil,1705mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.477mil]
Minimum Solder Mask Sliver Constraint: (0.378mil < 3.937mil) Between Pad U3-4(2097.716mil,1672.5mil) on Top Layer And Via (2055mil,1675mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [0.378mil]
Minimum Solder Mask Sliver Constraint: (3.821mil < 3.937mil) Between Pad U5-2(1791.339mil,1413.071mil) on Bottom Layer And Via (1775mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [3.821mil]
Minimum Solder Mask Sliver Constraint: (3.481mil < 3.937mil) Between Pad U5-3(1765.748mil,1413.071mil) on Bottom Layer And Via (1750mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [3.481mil]
Minimum Solder Mask Sliver Constraint: (0.818mil < 3.937mil) Between Pad U5-3(1765.748mil,1413.071mil) on Bottom Layer And Via (1775mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [0.818mil]
Minimum Solder Mask Sliver Constraint: (3.154mil < 3.937mil) Between Pad U5-4(1740.158mil,1413.071mil) on Bottom Layer And Via (1725mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [3.154mil]
Minimum Solder Mask Sliver Constraint: (0.963mil < 3.937mil) Between Pad U5-4(1740.158mil,1413.071mil) on Bottom Layer And Via (1750mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [0.963mil]
Minimum Solder Mask Sliver Constraint: (2.284mil < 3.937mil) Between Pad U5-40(1765.748mil,1859.921mil) on Bottom Layer And Via (1765mil,1825mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [2.284mil]
Minimum Solder Mask Sliver Constraint: (2.284mil < 3.937mil) Between Pad U5-41(1791.339mil,1859.921mil) on Bottom Layer And Via (1790mil,1825mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [2.284mil]
Minimum Solder Mask Sliver Constraint: (2.284mil < 3.937mil) Between Pad U5-42(1829.724mil,1859.921mil) on Bottom Layer And Via (1830mil,1825mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [2.284mil]
Minimum Solder Mask Sliver Constraint: (1.13mil < 3.937mil) Between Pad U5-5(1714.567mil,1413.071mil) on Bottom Layer And Via (1725mil,1380mil) from Top Layer to Bottom Layer [Dielectric 3] Mask Sliver [1.13mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1335mil,1355mil) from Top Layer to Bottom Layer And Via (1335mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1335mil,1355mil) from Top Layer to Bottom Layer And Via (1360mil,1355mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1335mil,1380mil) from Top Layer to Bottom Layer And Via (1360mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1360mil,1355mil) from Top Layer to Bottom Layer And Via (1360mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1435mil,920mil) from Top Layer to Bottom Layer And Via (1460mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1460mil,920mil) from Top Layer to Bottom Layer And Via (1485mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1485mil,920mil) from Top Layer to Bottom Layer And Via (1510mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1510mil,1085mil) from Top Layer to Bottom Layer And Via (1510mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1510mil,1085mil) from Top Layer to Bottom Layer And Via (1535mil,1085mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1510mil,1110mil) from Top Layer to Bottom Layer And Via (1535mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1510mil,920mil) from Top Layer to Bottom Layer And Via (1535mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1535mil,1085mil) from Top Layer to Bottom Layer And Via (1535mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1535mil,1085mil) from Top Layer to Bottom Layer And Via (1560mil,1085mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1535mil,1110mil) from Top Layer to Bottom Layer And Via (1560mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1535mil,920mil) from Top Layer to Bottom Layer And Via (1560mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1560mil,1085mil) from Top Layer to Bottom Layer And Via (1560mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1560mil,1085mil) from Top Layer to Bottom Layer And Via (1585mil,1085mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1560mil,1110mil) from Top Layer to Bottom Layer And Via (1585mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1560mil,920mil) from Top Layer to Bottom Layer And Via (1585mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1585mil,1085mil) from Top Layer to Bottom Layer And Via (1585mil,1110mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1585mil,920mil) from Top Layer to Bottom Layer And Via (1610mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1610mil,920mil) from Top Layer to Bottom Layer And Via (1635mil,920mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1725mil,1355mil) from Top Layer to Bottom Layer And Via (1725mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1725mil,1355mil) from Top Layer to Bottom Layer And Via (1750mil,1355mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1725mil,1380mil) from Top Layer to Bottom Layer And Via (1750mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1750mil,1355mil) from Top Layer to Bottom Layer And Via (1750mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1750mil,1355mil) from Top Layer to Bottom Layer And Via (1775mil,1355mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1750mil,1380mil) from Top Layer to Bottom Layer And Via (1775mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1135mil) from Top Layer to Bottom Layer And Via (1760mil,1160mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1135mil) from Top Layer to Bottom Layer And Via (1785mil,1135mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1160mil) from Top Layer to Bottom Layer And Via (1760mil,1185mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1160mil) from Top Layer to Bottom Layer And Via (1785mil,1160mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1185mil) from Top Layer to Bottom Layer And Via (1760mil,1210mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1185mil) from Top Layer to Bottom Layer And Via (1785mil,1185mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1210mil) from Top Layer to Bottom Layer And Via (1760mil,1235mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1210mil) from Top Layer to Bottom Layer And Via (1785mil,1210mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1235mil) from Top Layer to Bottom Layer And Via (1785mil,1235mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1585mil) from Top Layer to Bottom Layer And Via (1760mil,1610mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1585mil) from Top Layer to Bottom Layer And Via (1785mil,1585mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1610mil) from Top Layer to Bottom Layer And Via (1760mil,1635mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1610mil) from Top Layer to Bottom Layer And Via (1785mil,1610mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1635mil) from Top Layer to Bottom Layer And Via (1760mil,1660mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1635mil) from Top Layer to Bottom Layer And Via (1785mil,1635mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1660mil) from Top Layer to Bottom Layer And Via (1760mil,1685mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1660mil) from Top Layer to Bottom Layer And Via (1785mil,1660mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1760mil,1685mil) from Top Layer to Bottom Layer And Via (1785mil,1685mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1765mil,1825mil) from Top Layer to Bottom Layer And Via (1790mil,1825mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1770mil,1280mil) from Top Layer to Bottom Layer And Via (1795mil,1280mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1775mil,1355mil) from Top Layer to Bottom Layer And Via (1775mil,1380mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1135mil) from Top Layer to Bottom Layer And Via (1785mil,1160mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1160mil) from Top Layer to Bottom Layer And Via (1785mil,1185mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1185mil) from Top Layer to Bottom Layer And Via (1785mil,1210mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1210mil) from Top Layer to Bottom Layer And Via (1785mil,1235mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1585mil) from Top Layer to Bottom Layer And Via (1785mil,1610mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1610mil) from Top Layer to Bottom Layer And Via (1785mil,1635mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1635mil) from Top Layer to Bottom Layer And Via (1785mil,1660mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
Minimum Solder Mask Sliver Constraint: (1.063mil < 3.937mil) Between Via (1785mil,1660mil) from Top Layer to Bottom Layer And Via (1785mil,1685mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [1.063mil] / [Dielectric 3] Mask Sliver [1.063mil]
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Silk To Solder Mask (Clearance=5mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (3.7mil < 5mil) Between Area Fill (1134.103mil,877.401mil) (1145.914mil,885.275mil) on Top Overlay And Pad C21-2(1141.496mil,855mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.7mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Area Fill (2109.999mil,1188.003mil) (2129.999mil,1352.003mil) on Top Overlay And Pad U2-5(2111.732mil,1260mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (2.533mil < 5mil) Between Pad C12-1(1965mil,1233.071mil) on Top Layer And Track (1928.018mil,1248.661mil)(1928.018mil,1331.339mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.533mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C13-1(1983.622mil,1150mil) on Top Layer And Track (1985mil,1159.5mil)(2008mil,1159.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C13-2(1936.378mil,1150mil) on Top Layer And Track (1912mil,1159.5mil)(1935mil,1159.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C14-1(1983.622mil,1610mil) on Top Layer And Track (1985mil,1624.5mil)(2008mil,1624.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C14-2(1936.378mil,1610mil) on Top Layer And Track (1912mil,1624.5mil)(1935mil,1624.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C15-1(1983.622mil,1015mil) on Top Layer And Track (1985mil,1024.5mil)(2008mil,1024.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C15-2(1936.378mil,1015mil) on Top Layer And Track (1912mil,1024.5mil)(1935mil,1024.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C16-1(1983.622mil,1740mil) on Top Layer And Track (1985mil,1730.5mil)(2008mil,1730.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.927mil < 5mil) Between Pad C16-2(1936.378mil,1740mil) on Top Layer And Track (1912mil,1730.5mil)(1935mil,1730.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.927mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C17-1(1983.622mil,1045mil) on Top Layer And Track (1985mil,1035.5mil)(2008mil,1035.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C17-1(1983.622mil,1045mil) on Top Layer And Track (1985mil,1059.5mil)(2008mil,1059.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.927mil < 5mil) Between Pad C17-2(1936.378mil,1045mil) on Top Layer And Track (1912mil,1035.5mil)(1935mil,1035.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.927mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C17-2(1936.378mil,1045mil) on Top Layer And Track (1912mil,1059.5mil)(1935mil,1059.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C19-1(1983.622mil,1530mil) on Top Layer And Track (1985mil,1544.5mil)(2008mil,1544.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C19-2(1936.378mil,1530mil) on Top Layer And Track (1912mil,1544.5mil)(1935mil,1544.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (2.992mil < 5mil) Between Pad C20-1(1749.193mil,1784.252mil) on Top Layer And Track (1766.949mil,1721.024mil)(1766.949mil,1803.701mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.992mil]
Silk To Solder Mask Clearance Constraint: (2.992mil < 5mil) Between Pad C20-2(1749.193mil,1737.008mil) on Top Layer And Track (1766.949mil,1721.024mil)(1766.949mil,1803.701mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.992mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C3-1(2391.378mil,1645mil) on Top Layer And Track (2367mil,1630.5mil)(2390mil,1630.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C3-2(2438.622mil,1645mil) on Top Layer And Track (2440mil,1630.5mil)(2463mil,1630.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C6-1(2401.378mil,1125mil) on Top Layer And Track (2377mil,1139.5mil)(2400mil,1139.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C6-2(2448.622mil,1125mil) on Top Layer And Track (2450mil,1139.5mil)(2473mil,1139.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C7-1(2045mil,1536.378mil) on Top Layer And Track (2041.5mil,1273mil)(2041.5mil,1540mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad C7-1(2045mil,1536.378mil) on Top Layer And Track (2041.5mil,1540mil)(2050.496mil,1540mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad D1-2(2120mil,1502.008mil) on Top Layer And Track (2024.5mil,1512mil)(2065.5mil,1512mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.283mil < 5mil) Between Pad D1-2(2120mil,1502.008mil) on Top Layer And Track (2065.5mil,1512mil)(2065.5mil,1535mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.283mil]
Silk To Solder Mask Clearance Constraint: (4.984mil < 5mil) Between Pad D2-1(1150mil,1159.468mil) on Top Layer And Track (1117.5mil,1000mil)(1117.5mil,1175mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.984mil]
Silk To Solder Mask Clearance Constraint: (4.984mil < 5mil) Between Pad D2-2(1150mil,1030.532mil) on Top Layer And Track (1117.5mil,1000mil)(1117.5mil,1175mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.984mil]
Silk To Solder Mask Clearance Constraint: (4.984mil < 5mil) Between Pad D3-1(1075mil,1030.532mil) on Top Layer And Track (1107.5mil,1015mil)(1107.5mil,1190mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.984mil]
Silk To Solder Mask Clearance Constraint: (4.984mil < 5mil) Between Pad D3-2(1075mil,1159.468mil) on Top Layer And Track (1107.5mil,1015mil)(1107.5mil,1190mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.984mil]
Silk To Solder Mask Clearance Constraint: (1.889mil < 5mil) Between Pad L1-2(1880mil,1316.575mil) on Top Layer And Track (1869.5mil,1327mil)(1869.5mil,1350mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.889mil]
Silk To Solder Mask Clearance Constraint: (1.889mil < 5mil) Between Pad L1-2(1880mil,1316.575mil) on Top Layer And Track (1869.5mil,1327mil)(1910.5mil,1327mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.889mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad L1-2(1880mil,1316.575mil) on Top Layer And Track (1910.5mil,1327mil)(1910.5mil,1350mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.894mil < 5mil) Between Pad PGND-1(2022.5mil,571.5mil) on Top Layer And Text "PGND" (1875mil,642.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.894mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R10-1(1936.378mil,1565mil) on Top Layer And Track (1912mil,1550.5mil)(1935mil,1550.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R10-2(1983.622mil,1565mil) on Top Layer And Track (1985mil,1550.5mil)(2008mil,1550.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R1-1(2438.622mil,1610mil) on Top Layer And Track (2440mil,1624.5mil)(2463mil,1624.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R1-2(2391.378mil,1610mil) on Top Layer And Track (2367mil,1624.5mil)(2390mil,1624.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R2-1(2448.622mil,1160mil) on Top Layer And Track (2450mil,1145.5mil)(2473mil,1145.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R2-2(2401.378mil,1160mil) on Top Layer And Track (2377mil,1145.5mil)(2400mil,1145.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.927mil < 5mil) Between Pad R5-1(1936.378mil,1180mil) on Top Layer And Track (1912mil,1170.5mil)(1935mil,1170.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.927mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R5-2(1983.622mil,1180mil) on Top Layer And Track (1985mil,1170.5mil)(2008mil,1170.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R6-1(1983.622mil,1710mil) on Top Layer And Track (1985mil,1719.5mil)(2008mil,1719.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R6-2(1936.378mil,1710mil) on Top Layer And Track (1912mil,1719.5mil)(1935mil,1719.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R7-1(1983.622mil,1645mil) on Top Layer And Track (1985mil,1630.5mil)(2008mil,1630.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R7-2(1936.378mil,1645mil) on Top Layer And Track (1912mil,1630.5mil)(1935mil,1630.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R9-1(1983.622mil,1080mil) on Top Layer And Track (1985mil,1065.5mil)(2008mil,1065.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Pad R9-2(1936.378mil,1080mil) on Top Layer And Track (1912mil,1065.5mil)(1935mil,1065.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.894mil < 5mil) Between Pad TP2-1(1877.5mil,571.5mil) on Top Layer And Text "PGND" (1875mil,642.5mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.894mil]
Silk To Solder Mask Clearance Constraint: (4.33mil < 5mil) Between Pad U3-7(2097.716mil,1597.5mil) on Top Layer And Track (2024.5mil,1608mil)(2065.5mil,1608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [4.33mil]
Silk To Solder Mask Clearance Constraint: (2.853mil < 5mil) Between Pad U3-7(2097.716mil,1597.5mil) on Top Layer And Track (2065.5mil,1585mil)(2065.5mil,1608mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [2.853mil]
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